Siemens S7-1200PLC Motion Control Foundation - High Speed Counter

Aug 29, 2023

Siemens S7-1200PLC Motion Control Foundation - High Speed Counter

The counting process of the ordinary counter in PLC is related to the scanning operation mode. The CPU captures the rising edge of the measured signal by reading it once per scanning cycle. When the frequency of the measured signal is high, the counting pulse will be lost.

Therefore, the maximum operating frequency of ordinary counters is generally only a few tens of hertz. High speed counter (HSC) can count events that occur faster than the execution rate of program loop OB.


High speed counters are generally used in conjunction with incremental encoders, where each count pulse or reset pulse emitted by the latter serves as the input signal for the high speed counter. There are several types of encoders.

(1) Incremental encoder

The encoder disc of the photoelectric incremental encoder has uniformly engraved gratings. When the encoder rotates, it outputs pulses proportional to the increment of the rotation angle, and a counter is needed to count the number of pulses.

The single channel incremental encoder has only one pair of optocouplers inside, which can only generate one pulse train.

A dual channel incremental encoder, also known as an A/B phase or quadrature phase encoder, has two pairs of photosynthetic devices internally and outputs two independent pulse trains with a 90 ° difference.

The leading and lagging relationships of the two pulses during forward and reverse rotation are opposite. If an A/B phase encoder is used, the PLC can recognize the direction of shaft rotation and the output waveform of the A/B phase encoder.

Input points used by high-speed counters

The system manual of S7-1200 provides the default digital input points for HSCI-HSC6 of various CPU models when referring to humans in single-phase, two-phase, and A/B phases, as well as the highest counting frequency for each input point in different counting modes.

The data type of the actual count value of HSC1-HSC6 is DInt, and the default address is ID100-ID1020.

(1) The working mode of HSC

All HSCs have 5 high-speed counting operating modes: a single-phase counter with internal directional control, a timer with external directional length control, a biphase counter with two input channels of the clock, an AB phase orthogonal counter, and a monitoring P1O output. Each HSC mode can use or do not use a support input.

When the reset input is in the 1 state, the kinetic energy of the HSC's real count value can only start counting when it reaches the point where the reset input becomes the port.

The maximum measurable single pulse frequency is 100 kHz, and the maximum frequency for dual phase and A/B phase can be 30 kHz. The high-speed counter can be connected to an external rotary encoder, and users can use this function in software by configuring the PLC hardware and calling relevant instructions.

(1) Hardware Configuration of HSC

Open the device view of the PLC and select the CPU within it. Select the "General" high-speed counter HSC1 on the left side of the "Properties" tab in the inspection window, and check the checkbox "Enable this high-speed counter".

Select the 'Function' in the left window, set the 'Count Type' to 'Count', select the 'Work Mode' as the external direction control of the A/B phase counter, and set the initial counting direction to 'Add Count'.

Select "Hardware Input" in the left window and set the "Input for Clock Generator Phase A" address to 10.0, and the "Input for Clock Generator Phase B" address to 10.1. Select "I/O Address" in the left window. The default address of HSC1 is ID1000, which can be used to monitor the count value and hardware configuration of HSC1 during runtime.

(2) Set the filtering time for digital input

The default filtering time of the input filter for the digital input channels of the CPU and signal board is 6.4 ms. If the filtering time is too long, it is easy to filter out the input pulses during the filtering cycle.

For the digital input of high-speed counters, set the corresponding digital input filter using the expected minimum pulse width. The shorter filtering time in the input filtering time list for CPU digital input can be selected, such as 0.1 ms. If the width of the input pulse is changed, the filtering time of the input filter should also be changed.

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